CFI communicates with the C&DH system over a 1553B bus. The DPU acts as a remote terminal (RT) with the active C&DH system acting as the bus controller (BC). The traffic on the 1553B bus is periodic, repeating every one second major frame. The major frame is divided into 25 minor frames, numbered 0 to 24. Individual messages are distinguished by their transmit or receive subaddress. CFI handles only the messages described in Reference 3.
A collection of environmental data is collected by the DPU. There are analogs including voltages and currents read via one of the DPU's two Inter-Integrated Circuit (I2C) buses. A second I2C bus is used to collect temperatures. The data collected is included in the status subpacket and image headers. Each analog is also monitored when it is read (see below). Collection and monitoring occur once per second.
Alarms report problems found by the DPU software. Each alarm is described by an ID, two values, and a flag. The ID identifies the problem that has occurred and the accompanying values offer additional information. The flag indicates whether the alarm was caused by a transient or a persistent condition. See Appendix 2 for a list of alarms.
The alarms are divided into two groups: one for reporting internal software problems and another for reporting out-of-limit conditions for monitored data. Software problems are all reported as transient alarms. When the problem occurs, the alarm is generated and the software recovers from the problem as best it can.
Values read from the I2C buses are monitored by the DPU The monitoring is event driven: a monitor cycle is performed on each item as it becomes available. For example, each I2C analog is monitored when it is read. The monitoring algorithm is described in more detail in Reference 3.
The monitored data is summarized in the following table. The monitor
class is encoded as S=
shutdown,
N=nop, and R=redo. The reported alarm
Ids are for low and high excursions; similarly there are low and high
response
macro
Ids.
Source | Class | Alarm Ids Low / High | Macro Ids Low / High | ||
---|---|---|---|---|---|
CCD heater current | N | 128 | 192 | 0 | 2 |
DPU current | S | 129 | 193 | 1 | 1 |
DPU voltage | S | 130 | 194 | 1 | 1 |
Imager converter current | S | 131 | 195 | 5 | 5 |
HOP actuator #1 heater #1 current | N | 132 | 196 | 0 | 3 |
HOP actuator #1 heater #2 current | N | 133 | 197 | 0 | 3 |
Imager current | S | 134 | 198 | 5 | 5 |
HOP actuator #2 heater #1 current | N | 135 | 199 | 0 | 3 |
Imager voltage | S | 136 | 200 | 5 | 5 |
HOP actuator #2 heater #2 current | N | 137 | 201 | 0 | 3 |
FW motor primary current | N | 138 | 202 | 0 | 6 |
FW motor current | N | 139 | 203 | 0 | 6 |
FW motor converter current | N | 140 | 204 | 0 | 6 |
FW 15V current | N | 141 | 205 | 0 | 6 |
FW 15V voltage | S | 142 | 206 | 6 | 6 |
CM motor primary current | N | 143 | 207 | 0 | 4 |
CM motor current | N | 144 | 208 | 0 | 4 |
CM motor converter current | N | 145 | 209 | 0 | 4 |
CM 15V current | N | 146 | 210 | 0 | 4 |
CM 15V voltage | S | 147 | 211 | 4 | 4 |
CCD plate temperature #1 | N | 148 | 212 | 0 | 2 |
CCD plate temperature #2 | N | 149 | 213 | 0 | 2 |
Top bracket temperature | N | 150 | 214 | 0 | 0 |
Bottom bracket temperature | N | 151 | 215 | 0 | 0 |
M1/M2 tube base temperature | N | 152 | 216 | 0 | 0 |
Bench fold cube temperature | N | 153 | 217 | 0 | 0 |
Filter motor temperature | N | 154 | 218 | 0 | 0 |
Cube motor temperature | N | 155 | 219 | 0 | 0 |
Telescope tube bottom temperature | N | 156 | 220 | 0 | 0 |
Telescope tube top temperature | N | 157 | 221 | 0 | 0 |
Radiator temperature #2 | N | 158 | 222 | 0 | 2 |
Radiator temperature #1 | N | 159 | 223 | 0 | 2 |
Cover temperature #2 | N | 160 | 224 | 0 | 0 |
Cover temperature #1 | N | 161 | 225 | 0 | 0 |
Many of the DPU's hardware control registers contain triple redundancy and voting logic for each bit. The DPU software periodically rewrites these registers to correct single bit errors.
The DPU has a watchdog timer. If the watchdog timer is not tickled from time to time, the processor is reset. The watchdog timeout is 2.95 seconds. The watchdog does not run until it has been enabled; once enabled, it can never by disabled except by processor reset, watchdog or otherwise. The DPU monitors all periodic processes every second. If they are all running, the watchdog is tickled. Some aperiodic processes do not participate.
Return to CFI Software User's Guide. Report problems to John Hayes.